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| preliminary 4,000 usable pld gates with 82 i/os 300 mhz 16-bit counters, 400 mhz datapaths 0.35 m four-layer metal non-volatile cmos process for smallest die sizes 100% routable with 100% utilization and complete pin-out stability variable-grain logic cells provide high performance and 100% utilization comprehensive design tools include high quality verilog/vhdl synthesis !" # interfaces with both 3.3 v and 5.0 v devices pci compliant with 3.3 v and 5.0 v buses for -1/-2/-3/-4 speed grades full jtag boundary scan i/o cells with indivi dually controlled registered input path and output enables $ %&!" 74 bidirectional input/output pins, pci-compliant for 5.0 v and 3.3 v buses for -1/-2/-3/-4 speed grades four high-drive input-only pins four high-drive/distributed network pins '()*+) #' , )+ two array clock/control networks available to the logic cell flip-flop clock, set and reset inputs ? each driven by an input-only pin two global clock/control networks available to the logic cell; f1, clock, set and reset inputs and the data input, i/o register clock, reset and enable inputs as well as the output enable control ? each driven by an input- only or i/o pin, or any logic cell output or i/o cell feedback input + logic cell + output total delays under 6 ns data path speeds over 400 mhz counter speeds over 300 mhz -(.//0 *! . 1 * 02/// # (1 *! . 1 # preliminary & '") the ql3004e is a 4,000 usable pld gate memb er of the pasic 3 family of fpgas. pasic 3 fpgas are fabricated on a 0.35 m four-layer metal process using quicklogic ? 's patented vialink ? technology to provide a unique comb ination of high performance, high density, low cost, and extreme ease-of-use. the ql3004e contains 96 logic cells. with a m aximum of 74 i/os, the ql3004e is available 68-pin plcc, 84-pin plcc, and 100-pin tqfp packages. software support for the complete pasic 3 family, including th e ql3004e, is available through three basic packages. the turnkey quick works ? package provides the most complete fpga software solution from de sign entry to logic synthesis, to place and route, to simulation. the quicktools tm for workstations package provides a solution for designers who use cadence ? , exemplar tm , mentor ? , synopsys ? , synplicity ? , viewlogic tm , aldec tm , or other third-party tools for design entry, synthesis, or simulation. preliminary . * 3 4.5.32$ 4&6 7845//9 to calculate delays, multiply the appropriate k factor from $# : by the numbers provided in $# through $# 6 . *# 7 9 ' ! "##! $" %& ' ( ) *+* * * $# : & . 0 % t pd combinatorial delay b ( ( (( (( $,# - (( 1.4 1.7 1.9 2.2 3.2 t su setup time b 1.7 1.7 1.7 1.7 1.7 t h hold time 0.0 0.0 0.0 0.0 0.0 t clk clock to q delay 0.7 1.0 1.2 1.5 2.5 t cwhi clock high time 1.2 1.2 1.2 1.2 1.2 t cwlo clock low time 1.2 1.2 1.2 1.2 1.2 t set set delay 1.0 1.3 1.5 1.8 2.8 t reset reset delay 0.8 1.1 1.3 1.6 2.6 t sw set width 1.9 1.9 1.9 1.9 1.9 t rw reset width 1.8 1.8 1.8 1.8 1.8 preliminary 0 %, ./ 0 *# 7 9 ' ! "##! $"%& ' ( ) *+ * * * $# : & . 0 % & &0 t in high drive input delay 1.5 1.6 1.8 1.9 2.4 2.9 4.4 t ini high drive input, inverting delay 1.6 1.7 1.9 2.0 2.5 3.0 4.5 t isu input register set-up time 3.1 3.1 3.1 3.1 3.1 3.1 3.1 t ih input register hold time 0.0 0.0 0.0 0.0 0.0 0.0 0.0 t lclk input register clock to q 0.7 0.8 1.0 1.1 1.6 2.1 3.6 t lrst input register reset delay 0.6 0.7 0.9 1.0 1.5 2.0 3.5 t lesu input register clock enable set-up time 2.3 2.3 2.3 2.3 2.3 2.3 2.3 t leh input register clock enable hold time 0.0 0.0 0.0 0.0 0.0 0.0 0.0 # *# 7 9( ' ( %1( ( %2( * ( ( ( ( ( ( ( ( ( 3 ( & . 0 % / t ack array clock delay 1.2 1.2 1.3 1.3 1.5 1.6 1.7 t gckp global clock pin delay 0.7 0.7 0.7 0.7 0.7 0.7 0.7 t gckb global clock buffer delay 0.8 0.8 0.9 0.9 1.1 1.2 1.3 preliminary 6 1, ./ ,0/ *# 7 9 ' & . 0 % / t i/o input delay (bidirectional pad) 1.3 1.6 1.8 2.1 3.1 3.6 t isu input register set-up time 3.1 3.1 3.1 3.1 3.1 3.1 t ih input register hold time 0.0 0.0 0.0 0.0 0.0 0.0 t loclk input register clock to q 0.7 1.0 1.2 1.5 2.5 3.0 t lorst input register reset delay 0.6 0.9 1.1 1.4 2.4 2.9 t lesu input register clock enable set-up time 2.3 2.3 2.3 2.3 2.3 2.3 t leh input register clock enable hold time 0.0 0.0 0.0 0.0 0.0 0.0 ! "##! $"%& ' ( ) *+ * * * $# : &/ ./ ,0/ *# 7 9"' ' ( 7 9 ./ 6/ :6 // 6/ t outlh output delay low to high 2.1 2.5 3.1 3.6 4.7 t outhl output delay high to low 2.2 2.6 3.2 3.7 4.8 t pzh output delay tri-state to high 1.2 1.7 2.2 2.8 3.9 t pzl output delay tri-state to low 1.6 2.0 2.6 3.1 4.2 t phz output delay high to tri-state a 2.0 - - - - t plz output delay low to tri-state 1.2 - - - - ( ' & 45 1? 1? t phz t plz 5 pf 5 pf preliminary ; the dc specifications are provided in $# ; through $# % . 6$ ' 7 8 3 ' 3 ' v cc voltage -0.5 v to 4.6 v dc input current 20 ma v ccio voltage -0.5 v to 7.0 v esd pad protection 2000 v input voltage -0.5 v to v ccio +0.5 v storage temperature -65c to +150c latch-up immunity 200 ma lead temperature 300c 3/ 8 *# < ! ' < <= < <= < <= v cc supply voltage 3.0 3.6 3.0 3.6 3.0 3.6 v v ccio i/o input tolerance voltage 3.0 5.5 3.0 5.5 3.0 5.25 v ta ambient temperature -55 - -40 85 0 70 c tc case temperature - 125 - - - - c k delay factor -0 speed grade - - 0.43 1.90 0.46 1.85 n/a -1 speed grade 0.42 1.64 0.43 1.54 0.46 1.50 n/a -2 speed grade 0.42 1.37 0.43 1.28 0.46 1.25 n/a -3 speed grade 0.43 0.90 0.46 0.88 n/a -4 speed grade 0.43 0.82 0.46 0.80 n/a preliminary : 2 ( *# < <= v ih input high voltage 0.5 v cc v ccio +0.5 v v il input low voltage -0.5 0.3 v cc v v oh output high voltage ioh = -12 ma 2.4 v ioh = -500 a 0.9 v cc v v ol output low voltage iol = 16 ma a $ .0.%0.#0.1 ( ,. $ ( ( 2 $,/ 0.45 v iol = 1.5 ma 0.1 v cc v i i i or i/o input leakage current vi = v ccio or gnd -10 10 a i oz 3-state output leakage current vi = v ccio or gnd -10 10 a c i input capacitance b % ) 7 10 pf i os output short circuit current c / ( 7 #9 vo = gnd -15 -180 ma vo = v cc 40 210 ma i cc d.c. supply current d ) .0.%0.#0.1 ' 7 , # $ .9 * & $ ) $ * : ; ! < vi, vio = v ccio or gnd 0.50 (typ) 2 ma i ccio d.c. supply current on v ccio 0 100 a preliminary % 8 8 1 ! " # $% !& '$% 0.9200 0.9400 0.9600 0.9800 1.0000 1.0200 1.0400 1.0600 1.0800 1.1000 3 3.1 3.2 3.3 3.4 3.5 3.6 voltage factor vs. supply voltage supply voltage (v) kv 0.85 0.90 0.95 1.00 1.05 1.10 1.15 -60 -40 -20 0 20 40 60 80 temperature factor vs. operating temperature junction temperature c kt preliminary > )' *?' ( )* +,%' the following requirements must be me t when powering up the device (see ' 6 ). quicklogic recommends the following for the lowest poss ible power-up curren t. not following these recommendations will cause the device to draw more current during power-up: when ramping up the power supplies keep (v ccio -v cc ) max 500 mv. v ccio must lead v cc when ramping the device. the power supply must take greater th an or equal to 400 s to reach v cc . ramping to v cc /v ccio earlier than 400 s can cause the device to behave improperly. voltage v ccio v cc (v ccio -v cc ) max time 400 us v cc preliminary / @$ 1 -$ ./01% microprocessors and application specific integrated circuits (asics) pose many design challenges, not the least of which concerns the acce ssibility of test points . the joint test access group (jtag) formed in response to this chal lenge, resulting in ieee standard 1149.1, the standard test access port and boundary scan architecture. the jtag boundary scan test methodology allo ws complete observation and control of the boundary pins of a jtag-compa tible device through jtag software. a test access port (tap) controller works in concert with the instruction register (ir); these allow users to run three required tests, along with several user-defined tests. jtag tests allow users to reduce system debug time, reuse test platforms and tools, and reuse subsystem tests for fuller verification of higher level system elements. tck tms trstb rdi tdo instruction decode & control logic tap controller state machine (16 states) instruction register boundary-scan register (data register) mux bypass register mux internal register i/o registers user defined data register preliminary the 1149.1 standard requires the following three tests: extest instruction. the extest instruction performs a pcb interconnect test. this test places a device into an external boundary test mode, selecting the boun dary scan register to be connected between the tap's test data in (tdi) and test data out (tdo) pins. boundary scan cells are preloaded with test patterns (v ia the sample/preload instruction), and input boundary cells capture the input data for analysis. sample/preload instruction. this instruction allows a device to remain in its functional mode, while selecting the boundary scan regist er to be connected between the tdi and tdo pins. for this test, the boundary scan register can be accessed via a data scan operation, allowing users to sample the functional data entering and leaving the device. bypass instruction. the bypass instruction allows data to skip a device's boundary scan entirely, so the data pa sses through the bypass register. th e bypass instruction allows users to test a device without passing through othe r devices. the bypass register is connected between the tdi and tdo pins, allowing serial data to be transferred through a device without affecting the operation of the device. preliminary & = ' tdi test data in for jtag hold high during normal operation. connect to v cc if not used for jtag. trstb active low reset for jtag hold low during normal operation. connect to ground if not used for jtag. tms test mode select for jtag hold high during normal operation. connect to v cc if not used for jtag. tck test clock for jtag hold high or low during normal operation. connect to v cc or ground if not used for jtag. tdo test data out for jtag output that must be left unconnected if not used for jtag. stm special test mode must be grounded during normal operation. i/aclk high-drive input and/or array network driver can be configured as either or both. i/gclk high-drive input and/or global network driver can be configured as either or both. i high-drive input use for input signals with high fanout. i/o input/output pin can be configured as an input and/or output. v cc power supply pin connect to 3.3 v supply. v ccio input voltage tolerance pin connect to 5.0 v supply if 5 v input tolerance is required, otherwise connect to 3.3 v supply. gnd ground pin connect to ground. preliminary . " ! * contact quicklogic rega rding availability (see ! ) ql 3004e - 1 pf100 c quicklogic device pasic 3 device part number speed grade 0 = quick 1 = fast 2 = faster 3 = faster *4 = wow operating range c = commercial i = industrial m = military package code pl68 = 68-pin plcc pl84 = 84-pin plcc pf100 = 100-pin tqfp preliminary 0 ;%( ' 2 $ ) 3 ' ;%( ' $# 962 ;%( ' ;%( ' ;%( ' ;%( ' >? % ! .6 >? 6& ! & ,0/ > , .; ,0/ 6. , . ,0/ &/ >+0, .: ,0/ 60 >+0, 0 ! ,/ & ,0/ .% ,0/ 66 ,0/ 6 ,0/ && ,0/ .> ! ,/ 6; ,0/ ; ,0/ &. ,0/ 0/ ,0/ 6: ,0/ : ,0/ &0 ,0/ 0 ,0/ 6% ,0/ % ,0/ &6 ,0/ 0& 8 @ 6% ,0/ > / &; ,0/ 0. ' ;/ ,0/ / ,0/ &: , 00 ,0/ ; + ,0/ &% ,0/ 06 ,0/ ;& ' & ,0/ &> ,0/ 0; ,0/ ;. ,0/ . ,0/ ./ ,0/ 0: ,0/ ;0 ,0/ 0 >? . ,0/ 0% >? ;6 ,0/ 6 ,0/ .& ,0/ 0> ,0/ ;; ,0/ ; , .. ,0/ 6/ , ;: ,0/ : $+0, .0 ,0/ 6 $+0, ;% ,0/ tdo io io io io vccio io io gnd io io io io io io stm tck io io io io io io gclk/i i vcc aclk/i i io gnd io io io io tdi io io io io io io io gnd io io io vccio io io trstb tms 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 ql3004e-1pl68c pasic 3 io io io io gnd io i aclk/i vcc i gclk/i io io io io io io 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 preliminary 6 %0( ' 3 $ )3# ' %0( ' 21 %0( ' %0( ' %0( ' %0( ' ,0/ && $+0, 0. ,0/ ;0 $+0, & ,0/ &. , 00 ,0/ ;6 , . ,0/ &0 >+0, 06 ,0/ ;; >+0, 0 ! ,/ &6 ! 0; ! ,/ ;: ! 6 ,0/ &; ,0/ 0: ,0/ ;% ,0/ ; ,0/ &: ,0/ 0% ,0/ ;> ,0/ : ,0/ &% ,0/ 0> ,0/ :/ ,0/ % ,0/ &> ,0/ 6/ ,0/ : ,0/ > ,0/ ./ ,0/ 6 ,0/ :& ,0/ / ,0/ . ,0/ 6& 8 @ :. ,0/ / .& ,0/ 6. ' :0 ,0/ & ,0/ .. , 60 ,0/ :6 + . ,0/ .0 ,0/ 66 ,0/ :; ' 0 ,0/ .6 ,0/ 6; ,0/ :: ,0/ 6 ,0/ .; ! 6: ,0/ :% ,0/ ; ,0/ .: ,0/ 6% ,0/ :> ! : ,0/ .% ,0/ 6> ,0/ %/ ,0/ % ,0/ .> ,0/ ;/ ,0/ % ,0/ > >? 0/ >? ; >? %& >? &/ ,0/ 0 ,0/ ;& ,0/ %. ,0/ & , 0& ,0/ ;. , %0 ,0/ tdo io io io io io io vccio io io io io io gnd io io vcc io io stm tck io io io io io io io vcc gclk/i i aclk/i i io gnd io io io io io io io tdi io io vcc io io io gnd io io io io io vccio io io io io io trstb tms 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 ql3004e-1pf84c pasic 3 io io io io io io io gnd io i aclk/i i gclk/i vcc io io io io io io io 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 preliminary ; //$- ' 4 $ ) '$5 //$- ' $# %99 :) //$- ' //$- ' //$- ' //$- ' ,0/ &; , 6 ,0/ :; + & ,0/ &: ,0/ 6& ,0/ :: ' . ,0/ &% ,0/ 6. ,0/ :% ,0/ 0 ,0/ &> ,0/ 60 ,0/ :> ,0/ 6 ,0/ ./ ,0/ 66 ,0/ %/ ,0/ ; ,0/ . ,0/ 6; ,0/ % ,0/ : ,0/ .& ,0/ 6: ,0/ %& ,0/ % ,0/ .. ,0/ 6% ,0/ %. ,0/ > >? .0 ,0/ 6> >? %0 ,0/ / ,0/ .6 >? ;/ ,0/ %6 >? , .; ,0/ ; , %; ,0/ & $+0, .: ,0/ ;& $+0, %: ,0/ . ! .% >? ;. ! %% >? 0 , .> ,0/ ;0 , %> ,0/ 6 >+0, 0/ ,0/ ;6 >+0, >/ ,0/ ; ! 0 ,0/ ;; ! > ,0/ : ,0/ 0& ! ,/ ;: ,0/ >& ! ,/ % ,0/ 0. ,0/ ;% ,0/ >. ,0/ > ,0/ 00 ,0/ ;> ,0/ >0 ,0/ &/ ,0/ 06 ,0/ :/ ,0/ >6 ,0/ & ,0/ 0; ,0/ : ,0/ >; ,0/ && ,0/ 0: ,0/ :& ,0/ >: ,0/ pin 1 pin 26 pin 51 pin 76 ql3004e-1pf100c pasic 3 preliminary : &. ,0/ 0% ,0/ :. ,0/ >% ,0/ &0 ,0/ 0> 8 @ :0 ,0/ >> ,0/ &6 ,0/ 6/ ' :6 ,0/ // / %99 :) //$- ' //$- ' //$- ' //$- ' preliminary % ! telephone: 408 990 4000 (us) 416 497 8884 (canada) 44 1932 57 9011 (europe) 49 89 930 86 170 (germany) 852 8106 9091 (asia) 81 45 470 5525 (japan) e-mail: info@quicklogic.com support: support@quicklogic.com web site: http://www.quicklogic.com/ a $ +! copyright ? 2003 quicklogic corporation. all rights reserved. the information contained in this document and the accomp anying software programs is protected by copyright. all righ ts are reserved by quicklog ic corporation. quicklogic corporation reserves the right to modify this document without any obligation to notify any person or entity of such revision. copying, duplica ting, selling, or otherwis e distributing any part of this product without the prior written consent of an authorized representative of quicklogic is prohibited. quicklogic and the quicklogic logo, pasic, vialink, deskfab, and quickworks are registered trademarks of quicklogic corporation; ecli pse, quickfc, quickdsp, quickdr, quicksd, quicktools, quickcore, quickpro, spde, webasic, and webesp are trademarks of quicklogic corporation. #8 a a a january 2003 brian faith, andreea rotaru |
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